系统设想中的情势化体例 SCIE

期刊简介估计审稿时候： 12周，或约稿

The focus of this journal is on formal methods for designing, implementing, and validating the correctness of hardware (VLSI) and software systems. The stimulus for starting a journal with this goal came from both academia and industry. In both areas, interest in the use of formal methods has increased rapidly during the past few years. The enormous cost and time required to validate new designs has led to the realization that more powerful techniques must be developed. A number of techniques and tools are currently being devised for improving the reliability, and robustness of complex hardware and software systems. While the boundary between the (sub)components of a system that are cast in hardware, firmware, or software continues to blur, the relevant design disciplines and formal methods are maturing rapidly. Consequently, an important (and useful) collection of commonly applicable formal methods are expected to emerge that will strongly influence future design environments and design methods.

本期刊的重点是设想、实行和考证硬件（VLSI）和软件系统精确性的情势化体例。以此为方针开办期刊的念头来自学术界和产业界。在这两个范畴，人们对利用情势化体例的乐趣在曩昔几年中敏捷增添。考证新设想所需的庞大本钱和时候令人们认识到必须开辟更壮大的手艺。今朝正在设想很多手艺和东西来进步庞杂硬件和软件系统的靠得住性和妥当性。固然系统中硬件、固件或软件的（子）组件之间的边界延续恍惚，但相干的设想学科和情势化体例正在敏捷成熟。是以，估计将呈现一个主要（且有用）的经常使用情势化体例调集，这将对将来的设想环境和设想体例发生严重影响。

《Formal Methods In System Design》(系统设想中的情势化体例)编辑部通信体例为SPRINGER, VAN GODEWIJCKSTRAAT 30, DORDRECHT, NETHERLANDS, 3311 GZ。若是您须要辅佐投稿或润稿办事，您可以或许征询咱们的客服教员。咱们专一于期刊征询办事十年，熟习颁发政策，可为您供给一对一投稿指点，防止您在投稿时频仍碰鼻，节流您的可贵时候，有用晋升颁发机率，确保SCI检索（检索不了全额退款）。咱们视诺言为生命，多方面确保文章宁静失密，在任何环境下都不会泄漏您的小我信息或稿件内容。